As bits are programmed and erased in a nonvolatile memory array, the threshold voltage levels required to program and erase the memory cells shift due to electrical charge that cannot be erased being trapped in the gate structure above the channel region of the transistors forming the memory cells. This threshold voltage shift causes memory lifetime problems with reading the memory because a fixed reference voltage level is typically used in association with sensing (read) the memory. Examples of such a memory include nonvolatile memories such as nanocrystal memories, nitride memories and traditional floating gate nonvolatile memories. The operation of these memories is well documented in the literature and will not be described in detail herein.
For nitride and nanocrystal memories, electron charge accumulates in the gate structure that affects the channel's electrical characteristics. Shown in FIG. 1 is a graph that indicates a shift in the program threshold voltage and the erase threshold voltage due to the electron charge accumulation. As the number of memory program and erase cycles increases over the life of the memory, the accumulation of gate structure charge causes both the erase threshold voltage and the program threshold voltage to rise. Although the difference between the erase voltage and the program voltage may remain relatively the same over the life of the memory, the accumulation of charge results in a premature failure of the memory. A reference voltage, labeled “Reference”, is typically used to sense or read the memory. Whenever the erase threshold voltage exceeds this reference at a point in time 1, the memory can no longer be reliably read because the erase threshold voltage appears to be a program threshold voltage. The number of cycles at which this error may occur is variable and unpredictable.
Another failure issue associated with nitride and nanocrystal memories is the change in the value of the erase threshold voltage and the program threshold voltage as a function of time. Initially, nitride or nanocrystal memories have a relatively low erase threshold voltage and a higher program threshold voltage that differs by a predetermined amount. Between the program threshold voltage and the erase threshold voltage is a reference voltage that is used in a compare operation to sense or read the memory. As time proceeds, charge leakage from the gate structure of the transistors in the memory cells results in the program voltage decreasing as shown in the graph of FIG. 2. Also as time elapses, the erase threshold voltage of the memory increases due to one of several factors. Such factors include, for example, a phenomena known as ‘read disturb’ and/or ‘program disturb’ in which charge is added to the storage region of each memory cell. Another factor is caused by the loss of net positive charge in the storage region. As shown in FIG. 2, when the program threshold voltage declines to the value of the reference voltage at a point in time 2, operation of the memory becomes faulty because it is no longer possible to distinguish a program state from an erase state. Therefore, known nitride and nanocrystal memories have a finite operational life limited in time.
U.S. Pat. No. 6,011,725 entitled “Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping” by Eitan discloses a nitride memory with a single transistor having the capability of storing two bits by using asymmetrical charge trapping. The two bits are read from the transistor by comparing each bit with a reference voltage. Each bit is accessed from the transistor cell by switching the direction of current flow through the transistor. However, the memory is susceptible to the problem of the declining differential between the program threshold voltage and the erase threshold voltage and the increase of the erase threshold voltage above a reference voltage. Yet a further example of a nitride memory with a two-bit cell that is read by using a reference voltage is described in U.S. Pat. No. 6,181,597 entitled “EEPROM Array Using 2-Bit Non-Volatile Memory Cells With Serial Read Operations” by Nachumovsky. These memories are generally limited in useful life as a function of both time and the number of program/erase cycles.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.